In many high performance microprocessor systems, the system clock speed is faster than the memory or I/O access time. The conventional way to solve this problem is to have the CPU (central processing unit) wait for the memory access by waiting an incremental number of CPU clock cycles, such as 1 clock cycle (which is commonly known as "1 wait state") or 2 clock cycles ("2 wait states"). This, however, has the undesirable effect of slowing the system's processing speed. For example, for a 33 MHz 80386 CPU, the full CPU clock cycle is 30 nanoseconds and the CPU requires a minimum of just two CPU clock cycles per CPU bus cycle, which results in a minimum CPU bus cycle time of 60 nanoseconds. If the memory access time were 65 nanoseconds, for instance, this would require that 1 wait state be inserted which would produce a 90 nanosecond CPU bus cycle. The problem with wait stating the CPU in full CPU clock cycle increments is that in a case such as that just mentioned, while the CPU only needs to be slowed down by 5 nanoseconds it traditionally is slowed down by a full 30 nanoseconds due to the limited resolution available for wait stating the CPU.
Previously disclosed circuits have used clock stretching techniques to delay CPU cycles (see U.S. Pat. No. 5,045,715 issued Sept. 3, 1991, to Fitch), but these have only been able to stretch the clock pulse by increments of the 2.times. clock period (which is one half the period of the CPU clock for full in-phase clock stretching with one edge). This is particularly significant in that the period of the 2.times. clock is typically set to the maximum feasible speed for prevailing microprocessor technology (50-80MHz), such that a finer resolution could not be achieved by simply increasing the clock speed. In addition, previous clock stretching circuits have attempted to directly stretch both the 1.times. and 2.times. clocks.
FIGS. 1 and 2 are the same as FIGS. 1 and 3 of U.S. Pat. No. 5,045,715. The circuit of FIG. 1 is a clock circuit for generating two clock signals, one (CLK) having stretched clock phases on a cycle by cycle basis, and the second (2.times. CLK) being a clock signal having a frequency twice the frequency of the first clock signal which is phase and edge coherent with the first clock signal, including the stretched clock pulses. Shown are two JK flip-flops, an oscillator, a logic circuit, and an exclusive OR gate.
FIG. 2 shows the various signals used and generated by the circuit of FIG. 1. Note that signal A (CPUCLK) is phase coherent with the signal IN. The signal OUT is phase coherent with the signal CPUCLK.